1. Field of the Invention
The present invention relates to an active solid-state imaging device which effectively suppresses fixed-pattern noise.
2. Description of the Related Art
A solid-state imaging device which is called an active solid-state imaging device has been proposed, where signal charges generated in respective pixels are not directly read out, but they are amplified as voltages or currents in the respective pixels so that the amplified signal voltages or currents are read out via a scanning circuit.
In such an active solid-state imaging device, each pixel includes a photoelectric conversion section which generates a signal charge corresponding to incident light and an amplification section which amplifies the signal charge generated in the photoelectric conversion section as a signal voltage. The photoelectric conversion section and the amplification section may be arranged in the same plane or in layers. The pixel of the former type is called a horizontal type and that of the latter type is called a vertical type.
Pixels of an active pixel sensor (APS) as shown in FIG. 6 are known as an example of the horizontal-type pixel (see S. K. Mendis et al., "A 128.times.128 CMOS Active Pixel Image Sensor for Highly Integrated Imaging Systems", IEDM 93 (December 1993), pp. 583-586).
Referring to FIG. 6, a signal charge generated in a photoelectric conversion section 101 is transferred to the gate of a transistor 103 via a transistor 102 to be input into the transistor 103. The transistor 103 which is provided for impedance conversion amplifies the current of the signal. The output of the transistor 103 is read out as a signal voltage V.sub.sig via a pixel-selective transistor 104. After the signal voltage V.sub.sig has been output, a reset transistor 105 is turned on to discharge the signal charge accumulated in the gate of the transistor 103 to a drain V.sub.D.
Pixels of a charge modulation device (CMD) as shown in FIG. 7 are known as an example of the vertical-type pixel (see Nakamura et al., "Gate-accumulation Type MOS Phototransistor Image Sensor", Television Academy, Vol. 41, No. 11 (1987), pp. 1047-1053).
Referring to FIG. 7, a signal charge generated by photoelectric conversion is accumulated in the gate of a transistor 111 to which an initial voltage has been applied. During the readout period, a pulse voltage .phi..sub.X is applied to the gate of the transistor 111 to read out a signal voltage V.sub.sig at the transistor 111. During the discharge period, a pulse voltage .phi..sub.R which is higher than the pulse voltage .phi..sub.X is applied to the gate of the transistor 111 to discharge the signal charge in the gate to a substrate (not shown). Thus, the transistor 111 conducts all of the photoelectric conversion, the amplification of signal charge, and the pixel selection.
In the CMD-type pixel, however, three different voltage values need to be selectively applied to the gate of the transistor 111, and at least one of the three voltage values must be high.
In order to avoid the use of a high voltage, a type which can be driven only at low voltages has been proposed in Japanese Laid-Open Publication No. 8-78653 which has been filed by the same applicant as that of the present invention. This type of pixel is shown in FIG. 8, where a signal charge is accumulated in the gate of a transistor 121, and a pulse voltage .phi..sub.X is applied to the gate to read out a signal voltage V.sub.sig. During the discharge period, a pulse .phi..sub.R is applied to a transistor 122 to discharge the signal charge to a substrate shown as the grounding. With this configuration, both the pulse voltages .phi..sub.X and .phi..sub.R can be low. Thus, the driving with two low voltage values is possible.
All of the pixel configurations shown in FIGS. 6 to 8 can be represented by a common schematic view shown in FIG. 9. A photoelectric conversion section 131 not only conducts the photoelectric conversion, but also outputs a signal voltage in response to the pulse voltage .phi..sub.X and discharges the signal charge in response to the pulse voltage .phi..sub.R. An amplification section 132 amplifies the received signal voltage and outputs the amplified signal voltage as the signal voltage V.sub.sig.
FIG. 10 shows an example of an active solid-state imaging device having pixels with the above configuration.
Referring to FIG. 10, first horizontal scanning lines 143 extend from a first vertical scanning circuit 141, and second horizontal scanning lines 144 extend from a second vertical scanning circuit 142. The first and second horizontal scanning lines 143 and 144 and the vertical signal lines 140 cross each other, and pixels as shown in FIG. 9 are formed at the respective crossings of the lines.
The first vertical scanning circuit 141 sequentially selects the first horizontal scanning lines 143 to apply the pulse voltage .phi..sub.X to the photoelectric conversion sections 131 of the respective pixels via the selected first horizontal scanning lines 143. The photoelectric conversion sections 131 of the pixels of one horizontal row commonly connected to one first horizontal scanning line 143 receive the pulse voltage .phi..sub.X simultaneously, to output the respective signal voltages V.sub.sig to the corresponding vertical signal lines 140 via the amplification sections 132 of the pixels.
The second vertical scanning circuit 142 sequentially selects the second horizontal scanning lines 144 to apply the pulse voltage .phi..sub.R to the photoelectric conversion sections 131 of the respective pixels via the selected second horizontal scanning lines 144. The photoelectric conversion sections 131 of the pixels of one horizontal row commonly connected to one second horizontal scanning line 144 receive the pulse voltage .phi..sub.R simultaneously after the output of the respective signal voltages V.sub.sig to the corresponding vertical signal lines 140, to discharge the respective signal charges.
A correlated double sampling (CDS) circuit 147 is put in midway along each of the vertical signal lines 140 (see J. Hynecek, "A New Device Architecture Suitable for High Resolution and High Performance Image Sensors", IEEE Trans. Electron. Device, Vol. 35, No. 5 (May 1988), pp. 646-652).
The CDS circuit 147 receives the signal voltage V.sub.sig from the photoelectric conversion section 131 of each pixel. The CDS circuit 147 also receives a signal voltage V.sub.res from the photoelectric conversion section 131 of the pixel after the signal charge in the photoelectric conversion section 131 of the pixel has been discharged, to obtain the difference between the two signal voltages, i.e., the signal voltage V.sub.sig received during the readout period and the signal voltage V.sub.res received after the discharge period, and output a signal voltage representing the difference. By obtaining the difference between the signal voltage during the readout period and that after the discharge period for each pixel in this way, a threshold variation of the pixels (corresponding to the variation in the signal voltages after the discharge period) can be cancelled, and thereby fixed-pattern noise (FPN) caused by this variation can be suppressed.
The CDS circuit 147 includes a clamping circuit and a sample hold circuit. The clamping circuit has a clamping capacitor 149 and a clamping transistor 150. During the readout period, the signal voltage V.sub.sig from the photoelectric conversion section 131 of each pixel is input into the clamping capacitor 149. The clamping transistor 150 is turned on to convert the signal voltage V.sub.sig to a clamping voltage V.sub.VCP, and then turned off. After the discharge period when the signal charge in the photoelectric conversion section 131 of the pixel is discharged, the signal voltage V.sub.res from the photoelectric conversion section 131 of the pixel is input into the clamping capacitor 149, and a difference signal voltage [V.sub.VCP -(V.sub.sig -V.sub.res)] is obtained and held in the clamping circuit. If the clamping voltage V.sub.VCP is the grounding voltage, for example, a signal voltage [-(V.sub.sig -V.sub.res)] is held in the clamping circuit.
The sample hold circuit has a sampling transistor 151 and a source follower circuit drive transistor 152 for impedance conversion. After the formation of the difference signal voltage [-(V.sub.sig -V.sub.res)] by the clamping circuit, the sampling transistor 151 is turned on to allow the difference signal voltage [-(V.sub.sig -V.sub.res)] to be applied to the gate of the drive transistor 152. The drive transistor 152 is turned on, while holding the difference signal voltage [-(V.sub.sig -V.sub.res)] in the capacitance of the gate, to output the difference signal voltage [-(V.sub.sig -V.sub.res)] with an amplified current.
The above operation of the CDS circuit 147 is conducted for the respective pixels of one horizontal row. Thus, the difference signal voltages [-(V.sub.sig -V.sub.res)] based on the signal charges in the respective pixels of the horizontal row are output from the corresponding drive transistors 152.
The horizontal scanning circuit 145 sequentially turns on horizontal selective transistors 153 via vertical scanning lines 146. As the respective horizontal selective transistors 153 are sequentially turned on, the signal voltages [-(V.sub.sig -V.sub.res)] at the corresponding drive transistors 152 are sequentially transferred to a common signal line 154 via the horizontal selective transistors 153.
The common signal line 154 is connected at the output end thereof with a load transistor 155 which serves as a load for the drive transistors 152 and with transistors 156 and 157 which constitute a source follower circuit. The signal voltages [-(V.sub.sig -V.sub.res)] sequentially transferred from the respective drive transistors 152 to the common signal line 154 are output from a point between the transistors 156 and 157 as image signals OS.
FIG. 11 shows the timing of the signals used in the device shown in FIG. 10.
Referring to FIG. 11, a horizontal scanning period 1H is a period when the pixels of one horizontal row are scanned, i.e., the signal voltages at the pixels of one horizontal row are read out and transferred.
Pulse voltages .phi..sub.X (i), .phi..sub.X (i+1), .phi..sub.X (i+2), . . . , which determine the readout period for the respective horizontal rows of pixels, are output from the first vertical scanning circuit 141 to be sequentially applied to the first horizontal scanning lines 143. In response to the pulse voltages .phi..sub.X, the photoelectric conversion sections 131 of the pixels of each horizontal row output the respective signal voltages V.sub.sig.
Pulse voltages .phi..sub.R (i), .phi..sub.R (i+1), .phi..sub.R (i+2), . . . , which determine the discharge period for the respective horizontal rows of pixels, are output from the second vertical scanning circuit 142 to be sequentially applied to the second horizontal scanning lines 144. In response to the pulse voltages .phi..sub.R, the photoelectric conversion sections 131 of the pixels of each horizontal row discharge the respective signal charges.
A pulse voltage .phi..sub.VCP is applied to the respective clamping transistors 150, while a pulse voltage .phi..sub.VSH is applied to the respective sampling transistors 151. These pulse voltages .phi..sub.VCP and .phi..sub.VSH are applied during the readout periods before and after the discharge periods, respectively. With these pulse voltages, the signal voltage obtained from each pixel during the readout period is clamped, the difference between the clamped signal voltage and the signal voltage obtained from each pixel after the discharge period is calculated, and the signal voltage representing the difference is sampled and held.
Pulse voltages .phi..sub.H (j), .phi..sub.H (j+1), . . . , which determine the output of the signal voltages at the drive transistors 152, are sequentially applied to the horizontal selective transistors 153 from the horizontal scanning circuit 145 after the readout periods. In response to the pulse voltages .phi..sub.H, the signal voltages at the drive transistors 152 are sequentially transferred to the common signal line 154 via the respective horizontal selective transistors 153 to be finally output as the image signals OS.
Thus, the difference between the signal voltage obtained during the readout period and that obtained after the discharge period is calculated for each pixel, and the signal voltage representing the difference is output as the image signal OS. This effectively suppresses the fixed-pattern noise at the pixels caused by the threshold variation of the pixels.
However, although the fixed-pattern noise caused by the threshold variation of the pixels is suppressed, similar fixed-pattern noise arises due to a threshold variation of the drive transistors 152. This trouble has not yet been overcome.
The threshold variation of the drive transistors 152 is represented by a variation .DELTA.V.sub.T in the image signals OS.
The fixed-pattern noise caused by the threshold variation of the drive transistors 152 is common for pixels of a vertical column, though it is random horizontally on an image. As a result, a significant vertical stripe pattern is displayed on a screen, greatly degrading the display quality.
A variation in conductance also arises in the drive transistors 152, which results in a similar vertical stripe pattern.
In view of the foregoing, an objective of the present invention is to provide an active solid-state imaging device capable of greatly reducing the fixed-pattern noise caused by the drive transistors, i.e., transistors for holding and outputting sampled signal voltages.